1. Field of the Invention
The present invention relates to an electronic device and a control method for the electronic device, and more particularly, to an electronic device and a control method for the electronic device capable of eliminating input glitch.
2. Description of the Prior Art
In order to increase the writing or reading speed of synchronous dynamic random access memories (SDRAMs), double data rate three (DDR3) technology is introduced for related applications, where SDRAMs utilizing DDR3 technology can be referred to as DDR3 SDRAMs.
Please refer to FIG. 1. FIG. 1 shows a signal timing diagram of a clock signal CLK, a first data strobe signal DQS, a second data strobe signal DQS#, an input data strobe signal DQS_input, an input enable data strobe signal DQS_input enable, and an input chip data strobe signal DQS_input chip of the conventional Double Data Rate Three Synchronous Dynamic Random Access Memory (DDR3 SDRAM).
As shown in FIG. 1, when the conventional DDR3 SDRAM performs a reading operation (e.g. during the time period T0˜T3 in FIG. 1), the first data strobe signal DQS and the second data strobe signal DQS# will turn on the On-Die Termination (ODT) in the chip, so as to make the first data strobe signal DQS and the second data strobe signal DQS# stay in a voltage level of ½ VDD. Since the first data strobe signal DQS and the second data strobe signal DQS# are differential signals, when the first data strobe signal DQS and the second data strobe signal DQS# have the same voltage level, a glitch will be generated. Moreover, uncertainty of switch time of the input enable data strobe signal DQS_input enable will cause inputting the glitch, and thus the conventional DDR3 SDRAM has problems of catching wrong data due to the glitch.